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From the page:

"Why do this?

Through these reads and writes, we can get glimpses into the internal operation of the chip. Now for the 6502 this is a bit unnecessary, as the internal operations of the chip are already well known.

But there are many systems for which the inner workings are not well understood. This chiplab, initially tested with the 6502, should provide a way to learn and build models for these less well understood chips."

So, this is pretty much useless at its current state, a placeholder for introspecting more advanced, less known chips in the future. It's pretty much a "because we can" kind of system. And that's a darn fine excuse for building this.

Awesome work.

nes1.large instance class?

Based on the chiplab devboard, it's actually a 65c02. There is a difference. A lot of differences, actually.

https://emulationonline.com/shop/chiplab_6502/

Alternatively it's fairly trivial today to run a transistor-level simulation of the 6502 (and a couple of other chips) thanks to the visual6502 reverse engineering effort (the http: link is intended):

http://visual6502.org/

The netlist is available in their Git repo:

https://github.com/trebonian/visual6502

...and there's a C port of the netlist simulation code:

https://github.com/mist64/perfect6502

One advantage of this approach is that you can inspect internal chip state that isn't visible on the output pins, which is very useful for emulator coding.

...and a couple of years ago I glued all those bits and pieces together for a 'remix' of the original visual6502 web application, using WASM + WebGL + Dear Imgui:

https://floooh.github.io/visual6502remix/

Very awesome. Not sure what'd I'd ever use it for anything but it's cool to know the option exists.