HN Reader

> RISC-V has either little-endian or big-endian byte order.

Yeah though for instruction fetch it's always little endian. I honestly think they should remove support for big endian from the spec. As far as I know nobody has implemented it, the justification in the ISA manual is very dubious, and it adds unneeded complexity to the spec and to reference models.

Plus it's embarrassing (see Linus's rant which I fully agree with).

Just a heads-up that only the first three chapters are available so far. Apparently there will be ten, when finished.

It's not the right move, better do it in assembly. I have a little rv64 interprer written in x86_64 assembly.

Another way to build emulators that I am very interested in is to start from a spec, and automatically translate it into executable code. High-fidelity emulators have a lot of potential for testing and verification.

The best example I know of is Sail [1]. Among other, they have RISC-V spec [2] and a bunch of compiler back-ends. They can already generate C or OCaml emulators, and I have been working on a new Rust back-end recently.

[1]: https://github.com/rems-project/sail [2]: https://github.com/riscv/sail-riscv