> Normally, this kind of project would require approximately three months for a skilled human engineer (approximately 430 hours of work).
Creative marketing speak. Its most likely true in a corporate environment with a teams trying to coordinate their little fiefdoms, but not the case for a single engineer. Overestimated by ~one order of magnitude.
>With just one week of AI-powered processing, augmented by 38.5 hours of human expert assistance, the Project Speedrun computer was completed.
40 hours of human expert supervising. For reference https://www.kickstarter.com/projects/1714585446/chronos-14-h... You can watch layout process time lapse of the most difficult part of this products PCB by creator Tesla500 https://www.youtube.com/watch?v=41r3kKm_FME
"Total time to layout ~38 hours." - _13 years ago_, nowadays most of the things one would struggle back then got automated. 40 hours for Zync to DDR3 interface, what is left are power supplies and low speed stuff. Overview of the project https://www.youtube.com/watch?v=jU2aHMbiAkU
It took Ben almost as long to cleanup after AI as it took Tesla500 to design SOM from the ground up when DDR3 was still quite new and state of the art.
>Engineers preferred larger polygons for power distribution than Quilter originally produced. Enlarging these pours required opening space, shifting traces, and re-routing small regions to accommodate the changes.
No kidding, their tool generated nice fat power traces up to the first tight spot, and then gave up and bam 2mil tracks (VDDA_1V8 VDD_1V8) :D almost un-manufacturable at jlcpcb/pcbway (they have asterisks at 2mil) and very bad for power distribution (brownouts).
>The goal was to match human comfort levels for power-distribution robustness.
nah, in this particular case the goal was making it manufacturable and able to function at all. Human replaced those hilarious 2 mil traces with proper 15 mil ones. And you cant just click on a track and brrrrt it from 2 to 15mil as they themselves admit:
>Enlarging polygons often required freeing routing channels, which triggered additional micro-moves and refinements
Human EE had to go in, rip out more than half (the actually time consuming half) of the generated garbage and lay it out manually. Those "micro-moves" involved completely re-arranging layer stack moving whole swaths of signals to different layers, shuffling vias etc.
>Once via delays were included, several tuned routes no longer met their targets. The team re-balanced these nets manually.
"re-balanced" being colloquialism for ripped all the actually difficult to route parts and re-did manually.
AI didnt even try to length match flash. Just autorouted like you would 8MHz Arduino board.
ENET_TD2 - what the hell happened there? :D Signal is doing a loop/knot over itself while crossing 3 layers, Ben was probably too tired of AI shenanigans at this point and didnt catch it instead elongating ENET_TD1 to length match this lemon.
Comparing SOM AI output vs human "expert assistance" there is very little left from the AI. Almost every important track was touched/re-done from scratch by human hand. Ben (or another EE they didnt mention) did an amazing job salvaging this design into something actually working.
This is my impression after a quick glance. I didnt try looking for problems very hard, didnt look into component placement (caps, would required reading datasheets) or ran any FEM tools.
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