HN Reader

This is absolutely wild. Rendering graphics with just combinational logic and no frame buffer is the kind of constraint that breeds creativity.

The HAKMEM sine/cosine generator is such an elegant choice - it's numerically stable in fixed-point and requires only adds and bit-shifts. Perfect for hardware. I used a similar approach once for generating test patterns in an FPGA.

The fact that you can iterate on this in simulation, then deploy to actual silicon via Tiny Tapeout for $150 is honestly mind-blowing. We're living in the future.

I like how the grid pulses with the kick drum. Nice touch.

As a computer science guy who interlops in computer engineering i really want to find time to build something cool like this and tapeout. The retro architectures for rendering are simple but fun! I love the project

I was curious about the long-term stability of the cited HAKMEM sin/cos generator. I found an overview here: https://news.ycombinator.com/item?id=3111501 (EDIT: I'm still not sure about stability, apparently it is stable in exact arithmetic under certain conditions.) Coincidentally it is related to the Verlet integration video I posted last week: https://news.ycombinator.com/item?id=46253592

Reminds me of college: "Hardware and Software are logically equivalent"

Wow, nice work!! Coming from demo/intro coding where you have memory and a driver for audio(x86), this is very impressing.

Very impressive stuff. I used to frequent the JS demoscene, mostly dwitter - but this is on a whole other level.

Oh shit, this prompted me to check and turns out TinyTapeout is back to life! https://tinytapeout.com/

Reminds me of the time we repaired old pinball machines in trade school. Good times.

Really cool!

If you have registers, it's not "no memory".

>Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates

ok, but silicon is doped so it's slightly impure, and CPUs are also silicon and memory is also silicon.

you actually meant "4K gates, no clock, no synchronization, no timing" and maybe a little "not exactly sure when the output is rea... is rea... is ready"

Wow, I'm looking at current "Open Shuttles", a license to use 4KB of SRAM in the project is $2500. But it comes with Wishbone Bus interface!

> 1024x32 Commercial SRAM > CF_SRAM_1024x32 > Commercial SRAM: 1024 words x > 32 bits (4KB) with Wishbone Bus interface > Area: 0.17mm² > GPIOs: 0 > License: Commercial - $2500 per project

I'm tempted to put together an FPAA with Tiny Tapeout, but it likely won't fit in the allocated area.

No x, no y, just Z is a pattern so often used by chatGPT it has started to bleed into common usage by people who maybe aren't even using an LLM.